The present invention relates to a method of manufacturing a chip integrated substrate and more particularly to a method of manufacturing a chip integrated substrate which manufactures a chip integrated substrate having a chip provided between a pair of wiring boards.
At present, a performance of an electronic apparatus using a semiconductor device including a semiconductor chip has been enhanced, and it has been demanded to increase a density in the case in which a semiconductor chip is mounted on a substrate and to reduce a size and a space of the substrate mounting the semiconductor chip thereon.
Therefore, there has been proposed a substrate having a semiconductor chip embedded therein, that is, a so-called chip integrated type wiring board (hereinafter referred to as a chip integrated substrate), and there have been proposed various structures for causing the semiconductor chip to include the substrate.
An example of the chip integrated substrate is disclosed in Patent Document 1, for example. The chip integrated substrate disclosed in the Patent Document 1 is provided with a bump for functioning as a spacer between a first mounting substrate and a second mounting substrate, and has a structure in which a chip is mounted between a pair of substrates which are separated from each other through a bump. Moreover, there is employed a structure in which a sealing resin is provided between a pair of mounting substrates to protect the chip.
As a method of manufacturing the chip integrated substrate disclosed in the Patent Document 1, moreover, the semiconductor chip is first flip-flop mounted on the first mounting substrate and a bump functioning as a spacer is subsequently soldered to the first mounting substrate. Next, at least a portion in the vicinity of an apex of the bump is exposed onto the first mounting substrate and a sealing resin is formed to seal the chip.
When the sealing resin is formed, the second mounting substrate is laminated thereon to be electrically connected to the bump. Each of the processings is executed to manufacture the chip integrated substrate disclosed in the Patent Document 1.
[Patent Document 1] JP-A-2003-347722
The chip integrated substrate disclosed in the Patent Document 1 uses a method of flip-chip mounting a chip on the first mounting substrate. In case of a chip having a comparatively small number of terminals, however, the use of a wire bonding method can reduce a cost and can enhance an assembling property more greatly than that of a flip-chip mounting method.
On the other hand, in the method of manufacturing the chip integrated substrate disclosed in the Patent Document 1, the bump is provided on the first mounting substrate after the chip is mounted, and a soldering treatment is carried out at that time. In this case, a solder flux is applied to a soldering position of the bump of the first mounting substrate in a normal soldering treatment to enhance a wettability, thereby improving a reliability of a soldering bond, which is not particularly described in the Patent Document 1.
In the case in which the solder flux remains as a residue after the soldering, it causes a corrosion. For this reason, a cleaning treatment is carried out. In the cleaning treatment, the flux is reliably removed. Therefore, a cleaning solution is injected into a solder bonding position at a comparatively high flow velocity.
In the chip integrated substrate, however, a reduction in a size and space saving are implemented as described above, and the chip is mounted in the vicinity of a position in which the bump is provided in some cases. In these cases, when the chip is connected to the first mounting substrate by using the wire bonding method, there is a possibility that the cleaning solution might be injected onto a wire. In this case, there is a problem in that the wire is broken or the wire is deformed, resulting in the generation of a short circuit between adjacent wires.